Advanced Packaging Systems Made Easy

In order to make chip packaging flexible packaging manufacturers are having to develop advanced packaging systems to deal with the challenges in the coming years.

One of the most essential elements in Semiconductor design is the packaging. It is no secret though this is one of the hardest to master parts both technically & economically.

Since chips were developed packaging was from the start just simply a way to protect the device. It still does today but as technology advances and components become more sophisticated packaging has to step up and take on a much broader role.

This role needs to be strategic in that flexible packaging manufacturers must consider how new packaging is application specific and often forms a vital part of the system architecture.

It’s common to produce packaging that can channel heat, improve performance and reduce power and costs. With electronic packaging signal strength of components can even be improved by the packaging.

Advanced Packaging for Electronics
This advanced packaging is completely different from the typical plastic and ceramic solutions we commonly see. These types of materials are developed to enhance the reliability of semiconductor & node products as well being able to overcome the thermal and electrostatic limitations of legacy packaging films.

The best example of this is in multi-chip packaging. Here a third dimension enables processors to access memories using extremely fast connections. This significantly improves sending signals end to end across a large chip using just thin wires. With this method, heat will often build up and create resistance.

Here are some of the best-known packaging for digital and electronic products.

3D-IC
Some advantages of 2.5D & 3D IC Packaging include ultra-high routing density, ultra-high I/O density, homogeneous/heterogeneous memory, power and optics integration, interposer capable of embedding decoupling capacitor or active devices feasible and package reliability to meet automotive requirements.

With the ever-growing semiconductor content in electronic systems and the continually shrinking form factors of these products, it is becoming increasingly difficult to accommodate all of the required circuitry within the confines of a traditional two-dimensional (2D) IC package.

3D IC packaging overcomes these space limitations by stacking multiple dies within a single package. This approach provides a significant increase in the routing density and I/O count while also opening up new possibilities for integrating additional functionality into the package. 3D IC packaging also offers superior thermal characteristics compared to 2D solutions due to the increased surface area for heat dissipation.

In addition, 3D packaging can be used to create thinner and lighter products due to the reduced overall volume of the stacked dies.

Fan-out wafer-level packaging
An important factor in the industry’s transition from transistor scaling to system scaling and integration is fan-out wafer-level packaging (FOWLP). Instead of using a substrate, the architecture fanned out the chip interconnects across a redistribution layer. In comparison to wire bonds or flip-chip ball grid arrays (FCBGA), it produces a thinner package, reduced thermal resistance, and may cost less.

However, if the goal is to decrease costs by removing substrates, the truth is that this can result in warpage and die shifts, which would negate the cost savings. Improvements in lithography, pick-and-place, and molding procedures using either thermocompression or laser bonding are how engineers are solving die shifts.

However, problems like prolonged lead times for package substrates are hastening the implementation of FOWLP. Beyond the low pin count, power management fan-out wafer level structure that has historically been the major FOLWP application, it is noted that there are a few areas where there is an increased acceptance. These include mobile and high-performance computing/networking.

FOWLP is developing as an option. The most recent application processors from TSMC were used in Apple’s M1 Ultra chip instead of a substrate-based process (see figure 1). This is a component of a bigger trend. The market for fan-out packaging is anticipated to develop at a 15% compound annual growth rate and reach $3.4B in 2026.

System-in-package
Advanced packaging has been widely adopted by the semiconductor industry as a way to combat the limitations of Moore’s Law. As technology advances, wires become thinner and transistors shrink, meaning that signals must travel greater distances from one end of a chip to another. By connecting multiple chips using through-silicon vias, interposers, bridges, or simple wires that offer larger pipes for signalling, the speed of those signals can be increased while reducing energy consumption.

In addition, advanced packaging also allows engineers to have much more flexibility when mixing components developed at different process nodes to meet application requirements. By taking advantage of advanced packaging technologies, architects across the industry have been able to create designs that offer faster and more efficient performance.

As technology continues to evolve, advanced packaging will allow devices and systems to remain competitive on many fronts. Advanced packaging is a crucial element in this rapidly changing world where technological advancement requires a delicate balance between power consumption and performance metrics.

Future of Advanced Packaging
Advanced Packaging has been gaining momentum in recent years, particularly with server chips & mobile phones however there is just no commonality among solutions for it to be considered anything like mainstream.

The main reasons for this are –

• The vast majority of companies experimenting with advanced packaging have pushed performance boundaries. However, reductions in power to cost benefits have presented challenges. E.g. Moors Law.
• Most of the earlier implementations were bespoke designs that used nonstandard approaches and materials like MIL PRF 131 K and Def Stan 81-147 (formerly DEF STAN 81-75) Whilst most advanced packaging products were developed for known applications like mobile phones and network chips, most have been developed for very specific projects and use cases.
• The mainstream chip makers or rather those not at the cutting edge of chip & node research still have much room for manoeuvring concerning the power and performance ratios for established chips. This is made even more of a benefit because most manufacturers are adding optional extras to existing designs very quickly.

A consensus around advanced packaging is starting to be reached, however, the industry remains in flux and with constant changes forecast over the coming years it is incumbent upon flexible packaging manufacturers to experiment and develop new solutions to meet the challenges.